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Integrated Circuit Systems, Inc.
ICS1893 Brief
General
The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893 architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications. The ICS1893 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from killer packets. The ICS1893 provides a Serial Management Interface for exchanging command and status information with a Station Management (STA) entity. The ICS1893 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually (with input pins or control register settings) or automatically (using the A u t o - N eg o t i a t i o n f e a t u r e s ) . W h e n t h e I C S 1 8 9 3 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common.
Document Type: Brief Document Stage: Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiverTM
Features * Supports category 5 cables with attenuation in excess of * * * * * *
24 dB at 100 MHz across a temperature range from -5 to +85 C DSP-based baseline wander correction to virtually eliminate killer packets across temperature range of from -5 to +85 C Low-power, 0.35-micron CMOS (typically 400 mW) Single 3.3-V power supply. Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard 10Base-T and 100Base-TX IEEE 802.3 compliant Fully integrated, DSP-based PMD includes: - Adaptive equalization and baseline wander correction - Transmit wave shaping and stream cipher scrambler - MLT-3 encoder and NRZ/NRZI encoder - - - - - Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities
* Highly configurable design supports:
* MAC/Repeater Interface can be configured as:
- 10M or 100M Media Independent Interface - 100M Symbol Interface (bypasses the PCS) - 10M 7-wire Serial Interface
* Small Footprint 64-pin Thin Quad Flat Pack (TQFP)
ICS1893 Block Diagram
100Base-T 10/100 MII or Alternate MAC/Repeater Interface Interface MUX
PCS * Frame * CRS/COL Detection * Parallel to Serial * 4B/5B PMA * Clock Recovery * Link Monitor * Signal Detection * Error Detection TP_PMD * MLT-3 * Stream Cipher * Adaptive Equalizer * Baseline Wander Correction
Integrated Switch
10Base-T MII Extended Register Set Low-Jitter Clock Synthesizer Clock Power
TwistedPair Interface to Magnetics Modules and RJ45 Connector
MII Serial Management Interface
Configuration and Status
AutoNegotiation
LEDs and PHY Address
1893Brief Rev B 9/10/99
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
September, 1999
ICS1893 Data Sheet - Release
Chapter 3 ICS1893 Enhanced Features
Chapter 3 ICS1893 Enhanced Features
The ICS1893 is an enhanced version of the ICS1890. In contrast to the ICS1890, the ICS1893 offers significant improvements in both performance and features while maintaining backward compatibility. The specific differences between these devices are listed below. 1. The ICS1893 employs an advanced digital signal processing (DSP) architecture that improves the 100Base-TX Receiver performance beyond that of any other PHY in the market. Specifically: a. The ICS1893 DSP-based, adaptive equalization process allows the ICS1893 to accommodate a maximum cable attenuation/insertion loss in excess of 24 dB, which is nearly equivalent to the attenuation loss of a 100-meter Category 5 cable. b. The ICS1893 DSP-based, baseline-wander correction process eliminates killer packets. 2. The analog 10Base-T Receive Phase-Locked Loop (PLL) of the ICS1890 is replaced with a digital PLL in the ICS1893, thereby resulting in lower jitter and improved stability. 3. The ICS1890 Frequency-Locked Loop (FLL) that is part of the 100Base-TX Clock and Data Recovery circuitry is replaced with a digital FLL in the ICS1893, also resulting in lower jitter and improved stability. 4. The ICS1893 transmit circuits are improved in contrast to the ICS1890, resulting in a decrease in the magnitude of the 10Base-T harmonic content generated during transmission. (See ISO/IEC 8802-3: 1993 clause 8.3.1.3.) 5. The ICS1893 supports the Auto-Negotiation Next Page functions described in IEEE Std 802.3u-1995 clause 28.2.3.4. 6. The ICS1893 supports Management Frame (MF) Preamble Suppression. 7. The ICS1893 provides the Remote Jabber capability. 8. The ICS1893 has an improved version of the ICS1890 10Base-T Squelch operation. 9. The ICS1893 "seeds" (that is, initializes) the Transmit Stream Cipher Shift register by using the ICS1893 PHY address from Table 8-16, which minimizes crosstalk and noise in repeater applications. 10. The ICS1893 offers an automatic 10Base-T power-down mode. 11. The enhanced features of the ICS1893 required some modifications to the ICS1890 Management Registers. However, the ICS1893 Management Registers are backward-compatible with the ICS1890 Management Registers. Table 3-1 summarizes the differences between the ICS1890 and the ICS1893 Management Registers.
ICS1893 Rev B 9/10/99
Copyright (c) 1999, Integrated Circuit Systems, Inc. All rights reserved. 14
September, 1999
ICS1893 - Release
Table 3-1. Register. Bit(s) 1.6 3.9:4 3.3:0 6.2 7.15:0 8.15:0 9.15:0 through 15.15:0 ICS1890 Function Reserved Model Number Revision Number Next Page Able Not applicable (N/A) N/A IEEE reserved. Default 0b (always) 000010b 0011b 0b (always) N/A N/A 0000h
Chapter 3 ICS1893 Enhanced Features
Summary of Differences between ICS1890 and ICS1893 Registers ICS1893 Function Management Frame Preamble Suppression Model Number Revision Number Next Page Able Auto-Negotiate Next Page Transmit Register Auto-Negotiate Next Page Link Partner Ability IEEE reserved. Note: Although the default value is changed, this response more accurately reflects an MDIO access to registers 9-15. Remote Jabber Automatic 10Base-T Power Down ICS test registers. (There is no claim of backward compatibility for these registers.) 0b 000011b 0000b 1b 2001h 0000h FFFFh Default
18.15 19.1 20.15:0 through 31.15:0 Note:
Reserved Reserved N/A
0b 0b N/A
0b 1b See specific registers and bits.
1. There are new registers and bits. For example: a. Registers 7 and 8 are new (that is, the ICS1890 does not have these registers). b. Registers 20 through 31 are new ICS test registers. 2. For some bits (such as the model number and revision number bits), the default values are changed.
ICS1893 Rev B 9/10/99
Copyright (c) 1999, Integrated Circuit Systems, Inc. All rights reserved. 15
September, 1999
ICS1893 Data Sheet - Release
Chapter 4
Overview of the ICS1893
Chapter 4 Overview of the ICS1893
The ICS1893 is a stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control)/Repeater Interface, converts them into a serial bit stream, encodes them, and transmits them over the medium through an external isolation transformer. When receiving data, the ICS1893 converts and decodes a serial bit stream (acquired from an isolation transformer that interfaces with the medium) into sequential nibbles. It subsequently presents these nibbles to its MAC/Repeater Interface. The ICS1893 implements the OSI model's physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard:
* * * *
Physical Coding sublayer (PCS) Physical Medium Attachment sublayer (PMA) Physical Medium Dependent sublayer (PMD) Auto-Negotiation sublayer
The ICS1893 is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893 can interface directly to the MAC and offers multiple, configurable modes of operation. Alternately, this configurable interface can be connected to a repeater, which extends the physical layer of the OSI model. The ICS1893 transmits framed packets acquired from its MAC/Repeater Interface and receives encapsulated packets from another PHY, which it translates and presents to its MAC/Repeater Interface. Note: As per the ISO/IEC standard, the ICS1893 does not affect, nor is it affected by, the underlying structure of the MAC/repeater frame it is conveying.
ICS1893 Rev B 9/10/99
Copyright (c) 1999, Integrated Circuit Systems, Inc. All rights reserved. 16
September, 1999
ICS1893 Data Sheet - Release
Chapter 9
Pin Diagram, Listings, and Descriptions
Chapter 9 Pin Diagram, Listings, and Descriptions
9.1
ICS1893 Pin Diagram
REF_OUT
VDD_IO
VDD_IO
REF_IN
P4RD
P0AC
P1CL
P3TD
CRS 50
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NOD/REP 10/100SEL TP_CT VSS TP_TXP TP_TXN VDD VDD 10TCSR 100TCSR VSS VSS TP_RXP TP_RXN VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VSS 18 RESETn 19 MII/SI 20 21 22 23 24 25 26 27 28 29 30 31 32
49
COL
P2LI
VDD
VSS
VSS
VSS
VSS
48 47 46 45 44 43 42
TXD3 TXD2 TXD1 TXD0 TXEN TXCLK TXER RXTRI VSS RXER RXCLK VDD_IO RXDV RXD0 RXD1 RXD2
ICS1893
41 40 39 38 37 36 35 34 33
NC
LSTA
VSS
HW/SW
DPXSEL
VDD
ANSEL
LOCK
VSS
VSS
MDIO
MDC
RXD3
ICS1893 Rev B 9/10/99
Copyright (c) 1999, Integrated Circuit Systems, Inc. All rights reserved. 100
September, 1999
ICS1893 Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.4 DC Operating Characteristics
This section lists the ICS1893 DC operating characteristics.
10.4.1
DC Operating Characteristics for Supply Current
Table 10-4 lists the DC operating characteristics for the supply current to the ICS1893 under various conditions. Note: All VDD_IO measurements are taken with respect to VSS (which equals 0 V). DC Operating Characteristics for Supply Current Operating Mode 100Base-TX 10Base-T Auto-Negotiation Power-Down Reset Symbol IDD_IO IDD Supply Current Supply Current Supply Current Supply Current IDD_IO IDD IDD_IO IDD IDD_IO IDD IDD Min. - - - - - - - - - Typ. 8 110 5 150 5 80 3 40 50 Max. 11 125 8 160 8 90 5 50 60 Units mA mA mA mA mA mA mA mA mA
Table 10-4.
Parameter Supply Current
These supply current parameters are measured through VDD pins to the ICS1893. The supply current parameters include external transformer currents. Measurements taken with 100% data transmission and the minimum inter-packet gap.
10.4.2
DC Operating Characteristics for TTL Inputs and Outputs
Table 10-5 lists the 3.3-V DC operating characteristics of the ICS1893 TTL inputs and outputs. Note: All VDD_IO measurements are taken with respect to VSS (which equals 0 V). 3.3-V DC Operating Characteristics for TTL Inputs and Outputs Symbol VIH VIL VOH VOL VOH VOL Conditions VDD_IO = 3.47 V VDD_IO = 3.47 V VDD_IO = 3.14 V VDD_IO = 3.14 V VDD_IO = 3.14 V VDD_IO = 3.14 V - - IOH = -4 mA IOL = +4 mA IOH = -4 mA IOL = +4 mA Min. 2.0 - 2.4 - 2.4 - Max. - 0.8 - 0.4 - 0.4 Units V V V V V V
Table 10-5. Parameter
TTL Input High Voltage TTL Input Low Voltage TTL Output High Voltage TTL Output Low Voltage TTL Driving CMOS, Output High Voltage TTL Driving CMOS, Output Low Voltage
ICS1893 Rev B 9/10/99
Copyright (c) 1999, Integrated Circuit Systems, Inc. All rights reserved. 122
September, 1999
ICS1893 Data Sheet - Release
Chapter 12 Ordering Information
Chapter 12 Ordering Information
Figure 12-1 shows ordering information for the ICS1893 package:
* ICS1893Y-10
Figure 12-1. ICS1893 Ordering Information
ICS
1893
Y-10
Package Type Y-10 = 10 x 10 TQFP (Thin Quad Flat Pack)
Device Identifier
Company Identifier Integrated Circuit Systems, Inc.
ICS1893 Rev B 9/10/99
Copyright (c) 1999, Integrated Circuit Systems, Inc. All rights reserved. 148
September, 1999

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